89 lines
2.0 KiB
Plaintext
89 lines
2.0 KiB
Plaintext
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MEMORY {
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FLASH0 (rx) : ORIGIN = 0x08000000, LENGTH = 16K
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FLASH1 (rw) : ORIGIN = 0x08004000, LENGTH = 16K
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FLASH3 (rx) : ORIGIN = 0x08008000, LENGTH = 480K
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SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
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}
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PROVIDE(_stack = ORIGIN(SRAM) + LENGTH(SRAM));
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PROVIDE(_config = ORIGIN(FLASH1));
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stack_size = 40k;
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heap_size = 40k;
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_stack_start = ORIGIN(SRAM) + LENGTH(SRAM);
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_stack_end = _stack_start - stack_size;
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EXTERN (vector_table)
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ENTRY(reset_handler)
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SECTIONS {
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text : {
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*(.vectors)
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. = ALIGN(4);
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*(.rodata*)
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. = ALIGN(4);
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} >FLASH0
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.text : {
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*(.text*)
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. = ALIGN(4);
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} >FLASH3
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.preinit_array : {
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. = ALIGN(4);
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__preinit_array_start = .;
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KEEP (*(.preinit_array))
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__preinit_array_end = .;
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} >FLASH0
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.init_array : {
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. = ALIGN(4);
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__init_array_start = .;
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array))
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__init_array_end = .;
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} >FLASH0
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.fini_array : {
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. = ALIGN(4);
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__fini_array_start = .;
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KEEP (*(.fini_array))
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KEEP (*(SORT(.fini_array.*)))
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__fini_array_end = .;
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} >FLASH0
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. = ALIGN(4);
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_etext = .;
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.data : {
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_data = .;
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. = ALIGN(4);
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*(.data*)
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. = ALIGN(4);
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_edata = .;
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} >SRAM AT >FLASH0
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_data_loadaddr = LOADADDR(.data);
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.bss : {
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = .;
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} >SRAM
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. = ALIGN(4);
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.heap : {
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_heap_start = .;
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. = . + heap_size;
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_heap_end = .;
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} > SRAM
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. = ALIGN(4);
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_end = .;
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}
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