46 lines
1.9 KiB
Markdown
46 lines
1.9 KiB
Markdown
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## Minimal STM32 F4/F7 task sheduler
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NanoOS: "Make less makes no sense" =)
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### Register frame description
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```
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/*
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* ABI: r0..r3 are caller-saved (scratch registers), R4..R12 are callee-saved.
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* It is appropriate to use R12 for a system call opcode (saved by NVIC). The
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* stack pointer points to the current extent of the stack -- it is decremented
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* before being used as index in a store. The stack grows downwards, to lower
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* addresses. When an interrupt is processed, 8 registers are stored. LR is set
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* to a special value that makes an ordinary function return into a return from
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* interrupt. The LR value indicates which stack is going to be used (process
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* or main) and can be modified before return.
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*
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* ____________________
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* Stack | |
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* | |
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* higher | R4 | <-- SP saved in TCB (64B context)
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* addresses | R5 | ^
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* | ^ | R6 | |
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* | | | R7 | | 8 registers pushed by handler:
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* | | | R8 | | R4..R11
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* | | | R9 | | Full task context is now stored
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* V | | R10 | |
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* | | R11 | |
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* direction | R0 | <-- SP when SVC handler gets control
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* of growth | R1 | ^
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* | R2 | |
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* | R3 | | 8 registers are pushed by
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* | R12 | | the NVIC hardware:
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* | LR (R14) | | xPSR, PC, LR, R12, R3..R0
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* | PC (R15) | |
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* | xPSR | |
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* | | <-- SP before SVC
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* | (stuff) |
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* Stack + | |
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* StackSize |____________________|
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*
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*/
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```
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