/* * Copyright 2017 Oleg Borodin */ #include #include #include void contr_adc_init() { /* Disable ADC */ REG_SETDOWN_BIT(ADCSRA, ADEN); /* Set reference*/ REG_SETUP_BIT(ADMUX, REFS0); REG_SETDOWN_BIT(ADMUX, REFS1); /* Set result type */ REG_SETUP_BIT(ADMUX, ADLAR); /* Set freq prescale */ REG_SETUP_BIT(ADCSRA, ADPS2); REG_SETUP_BIT(ADCSRA, ADPS1); REG_SETUP_BIT(ADCSRA, ADPS0); /* Disable autoconversion */ REG_SETDOWN_BIT(ADCSRA, ADATE); /* Disable interrupt */ REG_SETDOWN_BIT(ADCSRA, ADIE); /* Enable ADC */ REG_SETUP_BIT(ADCSRA, ADEN); } void contr_timer_init(void) { /* Disable comparators */ REG_SETDOWN_BIT(TCCR0A, COM0A1); REG_SETDOWN_BIT(TCCR0A, COM0A0); REG_SETDOWN_BIT(TCCR0A, COM0B1); REG_SETDOWN_BIT(TCCR0A, COM0B0); /* Set normal mode */ REG_SETDOWN_BIT(TCCR0A, WGM01); REG_SETDOWN_BIT(TCCR0A, WGM00); /* Set clock to 1/64 */ REG_SETDOWN_BIT(TCCR0B, CS02); REG_SETUP_BIT(TCCR0B, CS01); REG_SETUP_BIT(TCCR0B, CS00); /* Enable timer interrupt */ REG_SETUP_BIT(TIMSK0, TOIE0); //REG_SETUP(TCNT0, TIMER_INITVAL); }